Solid state CCD image sensors often employ a double polysilicon gate structure to form a gate electrode array structure. Such a structure has first polysilicon gate electrodes separated from second polysilicon gate electrodes by a thin insulating layer of silicon dioxide. The first polysilicon electrode is slightly overlapped by the second polysilicon electrode. The systematic variations of potential applied to these electrodes, referred to as clocking, permits the device to function. In the case of a frame transfer CCD image sensor, light passes through the polysilicon electrodes and creates electronic hole pairs in the underlying silicon. By clocking electrodes, the accumulated electrons are moved under adjacent electrodes. Light must pass through the polysilicon electrodes in order to accumulate charge. However, polysilicon is not entirely transparent. This lack of transparency results in the reduction of sensitivity and spectral response of the image sensor.
Due to its transparency, it has been recognized that indium tin oxide would be an effective electrode for such a device. The use of indium tin oxide electrodes enhances the blue response and overall sensitivity of a frame transfer image sensor. In fact, it has been recognized that if indium tin oxide were to be used in such a device, the effective ASA of the device could be increased by as much as a factor of two. One reason that indium tin oxide has not been used on such devices is because it is difficult to pattern such materials. Indium tin oxide gate electrode structures are generally not effective in schemes which use overlapping gate electrodes. This is due to the fact that generally the first gate electrode needs to provide isolation from the second gate electrode and ITO does not oxidize to produce an insulating layer.
Of course, if an ITO planar gate electrode CCD image sensor could be provided, then the electrodes would not need to overlap. Also, there would be no need to oxidize the gate material for electrical insulation. All that would be necessary would be to deposit a dielectric which provides isolation of the gates from metal interconnects.
The difficulty in creating ITO planar electrode structures for CCD applications, is in the patterning of sub-micron gaps between ITO gates. For a planar ITO gate CCD to function, the gate electrodes must be easily spaced at a sub-micron distance in order to assure effective charge transfer efficiency.